 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| 74F673A 16-Bit Serial-In, Serial/Parallel-Out Shift Register April 1988 Revised October 2000 74F673A 16-Bit Serial-In, Serial/Parallel-Out Shift Register General Description The 74F673A contains a 16-bit serial-in, serial-out shift register and a 16-bit Parallel-Out storage register. A single pin serves either as an input for serial entry or as a 3-STATE serial output. In the Serial-Out mode, the data recirculates in the shift register. By means of a separate clock, the contents of the shift register are transferred to the storage register for parallel outputting. The contents of the storage register can also be parallel loaded back into the shift register. A HIGH signal on the Chip Select input prevents both shifting and parallel transfer. The storage register may be cleared via STMR. Features s Serial-to-parallel converter s 16-bit serial I/O shift register s 16-bit parallel-out storage register s Recirculating serial shifting s Recirculating parallel transfer s Common serial data I/O pin s Slim 24 lead package Ordering Code: Order Number 74F673ASC 74F673APC 74F673ASPC Package Number M24B N24A N24C Package Description 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-011, 0.600 Wide 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Devices also available in Tape and Reel. Specify by appending the suffix letter "X" to the ordering code. Logic Symbols IEEE/IEC Connection Diagram (c) 2000 Fairchild Semiconductor Corporation DS009585 www.fairchildsemi.com 74F673A Unit Loading/Fan Out Pin Names CS SHCP STMR STCP R/W SI/O Q0-Q15 Description Chip Select Input (Active LOW) Shift Clock Pulse Input (Active Falling Edge) Store Master Reset Input (Active LOW) Store Clock Pulse Input Read/Write Input Serial Data Input or 3-STATE Serial Output Parallel Data Outputs U.L. HIGH/LOW 1.0/1.0 1.0/1.0 1.0/1.0 1.0/1.0 1.0/1.0 3.5/1.0 150/40 50/33.3 Input IIH/IIL Output IOH/IOL 20 A/-0.6 mA 20 A/-0.6 mA 20 A/-0.6 mA 20 A/-0.6 mA 20 A/-0.6 mA 70 A/-0.6 mA -3 mA/24 mA -1 mA/20 mA Functional Description The 16-bit shift register operates in one of four modes, as indicated in the Shift Register Operations Table. A HIGH signal on the Chip Select (CS) input prevents clocking and forces the Serial Input/Output (SI/O) 3-STATE buffer into the high impedance state. During serial shift-out operations, the SI/O buffer is active (i.e., enabled) and the output data is also recirculated back into the shift register. When parallel loading the shift register from the storage register, serial shifting is inhibited. The storage register has an asynchronous master reset (STMR) input that overrides all other inputs and forces the Q0-Q15 outputs LOW. The storage register is in the Hold mode when either CS or the Read/Write (R/W) input is HIGH. With CS and R/W both LOW, the storage register is parallel loaded from the shift register. Shift Register Operations Table Control Inputs CS R/W SHCP STCP H L L X L H X X X L SI/O Operating Mode Status High Z Data In Hold Serial Load Storage Register Operations Table Control Inputs STMR L H H H CS X H X L R/W X X H L STCP X X Operating Mode Reset; Outputs LOW Hold Hold Parallel Load L H Data Out Serial Output with Recirculation H Active Parallel Load; No Shifting H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial = HIGH-to-LOW Transition H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial = LOW-to-HIGH Transition X www.fairchildsemi.com 2 74F673A Block Diagram 3 www.fairchildsemi.com 74F673A Absolute Maximum Ratings(Note 1) Storage Temperature Ambient Temperature under Bias Junction Temperature under Bias VCC Pin Potential to Ground Pin Input Voltage (Note 2) Input Current (Note 2) Voltage Applied to Output in HIGH State (with VCC = 0V) Standard Output 3-STATE Output Current Applied to Output in LOW State (Max) twice the rated IOL (mA) -65C to +150C -55C to +125C -55C to +150C -0.5V to +7.0V -0.5V to +7.0V -30 mA to +5.0 mA Recommended Operating Conditions Free Air Ambient Temperature Supply Voltage 0C to +70C +4.5V to +5.5V -0.5V to VCC -0.5V to +5.5V Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. Note 2: Either voltage limit or current limit is sufficient to protect inputs. DC Electrical Characteristics Symbol VIH VIL VCD VOH Parameter Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage Output HIGH Voltage 10% VCC 10% VCC 5% VCC 5% VCC VOL IIH IBVI IBVIT IIL IIH + IOZH IIL + IOZL IOS ICEX IZZ ICCH ICCL Output LOW Voltage Input HIGH Current Input HIGH Current Breakdown Test Input HIGH Current Breakdown Test (I/O) Input LOW Current Output Leakage Current Output Leakage Current Output Short-Circuit Current Output HIGH Leakage Current Bus Drainage Test Power Supply Current Power Supply Current 114 114 -60 10% VCC 10% VCC 2.5 2.4 2.7 2.7 0.5 0.5 20 100 1.0 -0.6 70 -650 -150 250 500 172 172 V A A mA mA A A mA A A mA mA Min Max Max Max Max Max Max Max Max 0.0V Max Max V Min Min 2.0 0.8 -1.2 Typ Max Units V V V Min VCC Conditions Recognized as a HIGH Signal Recognized as a LOW Signal IIN = -18 mA (Non I/O pins) IOH = -1 mA (Qn, SI/O) IOH = -3 mA (SI/O) IOH = -1 mA (Qn, SI/O) IOH = -3 mA (SI/O) IOL = 20 mA (Qn) IOL = 24 mA (SI/O) VIN = 2.7V (Non I/O pins) VIN = 7.0V (Non I/O pins) VIN = 5.5V (SI/O) VIN = 0.5V VOUT = 2.7V (SI/O) VOUT = 0.5V (SI/O) VOUT = 0V VOUT = VCC VOUT = 5.25V VO = HIGH VO = LOW www.fairchildsemi.com 4 74F673A AC Electrical Characteristics TA = +25C Symbol Parameter Min fMAX tPLH tPHL tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ tPZH tPZL tPHZ tPLZ Maximum Clock Frequency Propagation Delay STCP to Qn Propagation Delay STMR to Qn Propagation Delay SHCP to SI/O Output Enable Time CS to SI/O Output Disable Time CS to SI/O Output Enable Time R/W to SI/O Output Disable Time R/W to SI/O 100 3.0 3.0 6.0 4.0 4.5 5.0 5.5 3.5 3.0 4.5 4.5 3.0 2.5 VCC = +5.0V CL = 50 pF Typ 130 8.0 10.5 16.5 6.5 8.0 8.5 9.0 5.5 4.5 7.5 8.0 5.5 4.0 10.5 13.5 20.5 8.5 10.5 11.0 11.5 7.5 6.5 9.5 10.0 7.0 5.5 Max TA = 0C to +70C VCC = +5.0V CL = 50 pF Min 85 2.5 2.5 5.5 3.5 4.0 4.0 4.5 3.0 2.5 4.0 4.0 2.5 2.0 12.0 15.0 22.5 9.5 12.0 12.5 13.0 8.5 7.5 10.5 11.5 8.0 6.5 ns ns Max MHz ns ns ns Units AC Operating Requirements TA = +25C Symbol Parameter VCC = +5.0V Min tS(H) tS(L) tH(H) tH(L) tS(H) tS(L) tH(H) tH(L) Setup Time, HIGH or LOW CS or R/W to STCP Hold Time, HIGH or LOW CS or R/W to STCP Setup Time, HIGH or LOW SI/O to SHCP Hold Time, HIGH or LOW SI/O to SHCP 3.5 6.0 0 0 3.0 3.0 3.0 3.0 Max TA = 0C to +70C VCC = +5.0V Min 4.0 7.0 0 0 3.5 3.5 3.5 3.5 ns ns Max Units 5 www.fairchildsemi.com 74F673A Physical Dimensions inches (millimeters) unless otherwise noted 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide Package Number M24B 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-011, 0.600 Wide Package Number N24A www.fairchildsemi.com 6 74F673A 16-Bit Serial-In, Serial/Parallel-Out Shift Register Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Package Number N24C Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 7 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com www.fairchildsemi.com |
Price & Availability of 74F673A
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |